1. Field of the Invention
The present invention relates to a double-buffered time division switching system for use in a network capable of simultaneously handling telephone exchange service and non-telephone service including high speed and wide band communication service.
2. Description of the Prior Art
A time division switching system switches connections between two channels of two different time division multiplex communication paths.
Known time division time switches utilize a memory switch and a control memory. Input signals on the channels on a number of input lines, for instance N lines, are written into the memory switch. The signals are then read out in a prescribed sequence (which is different from the sequence of the writing of the input signals into this memory switch) the read out signals are output into the channels on the N different output lines. This enables a connection of the N communication lines connected to the output side with the N communication lines connected on the input side in any desired combination on a channel basis.
The control memory is used to supply read addresses for the memory switch. Read addresses for the N lines, i.e., N such addresses, are written into the control memory and read out in a prescribed sequence and then are supplied to the memory switch.
To change the connection between channels, the corresponding read address written into the control memory is altered.
A frame is a round of actions to sequentially store all the signals for the N lines and to read these signals for the N lines in a prescribed sequence with the memory switch. If the time length of this single frame is selected to be 125 microseconds and signals for a single line (or a single channel) are eight-bit digital signals, 8 (bits)/125 (microseconds)=64K bits are switched (for instance in a telephone exchange) per second per line. Such a process of switching will be hereinafter referred to as 64K b/s switching.
However, if data transmission is to be achieved through a data terminal having a transmission speed which is higher than 64K b/s which is connected to a 64K b/s switching system, a series of data will be split into two or more time slots within a frame and will be separately transmitted (two time slots are used if the bit rate is 64K b/s.times.2=128K b/s). Since these separate groups of data have close relations and continuity among one another within the same frame, they have to be within the same frame when inputted or output by a time division switch. However, since a conventional time division switch cannot preserve the same sequence of signals on the input side and the output side, high speed data switching cannot be achieved in such an instance unless some special arrangement is made.
The following description concerns, as an example, a case in which a multiplex-time-division communication path of 128 channels per frame is handled with a time division switch.
FIG. 1 illustrates a typical three-stage time division switching system having a primary switch PSW (time division switch), a secondary switch (space division switch) and a tertiary switch TSW (time division switch). In the time division switches constituting the primary and tertiary switches, eight-bit data of one of the 128 channels is allocated for each time slot on the input slot. This eight-bit data is inserted into any desired time slot on the output side to be output.
If, as illustrated in FIG. 2(a), there are two mutually related data X1 (8 bits) and X2 (8 bits), i.e., two data of 64K b/s.times.2, belonging to a single frame in input time slots (ITS's) No. 0 and No. 4, respectively, and if the data X1 and X2 are inserted into unoccupied output time slots (OTS's) No. 0 and No. 6, respectively, selected by the time division switch, to be output, these data X1 and X2 will be output in the same frame so that their relativity will be preserved. However, if OTS No. 0 and No. 1 are selected, as shown in FIG. 2(b), for outputting two 64K b/s data X1 and X2, respectively, the data X2 cannot be written into the memory switch in time for its read out (insertion into OTS No. 1), so that the data X2 in the preceding frame (a cycle before) will always be output into OTS No. 1. Then, the sequence between the data X1 and X2 cannot be preserved. The relativity between them cannot be maintained at the data terminal on the receiving side. If the algorithm of software is designed to so select OTS's in the time division switch as to read out the data after their writing into the memory switch always within the same frame, as shown in FIG. 2(a), the sequence and relativity will be preserved even in such switching of 64K b/s.times.2. However, it will invite increases in the time required for the processing of an unoccupied time slot selection and in the block ratio, resulting in a reduction of the processing capacity of the switching system.
Meanwhile, U.S. Pat. No. 3,967,070 discloses an example of a double-buffered time division switch in which two memory switches are used, one in the read mode when the other is in the write. The two memory-switches are alternately switched back and to forth. A use of such a time division switch for switching 64K b/s.times.n data, as referred to above, would make it possible to preserve the sequence and relativity among the data.
However, the control which switches the modes of the two memories in a strictly periodic way entails the following problem. Where 64K b/s speech signals are switched with such switches, depending on the relationship between a write time W and a read time R determined commonly for two memories A and B, the length of time T taken by each memory from the write time W until the read time R, as shown in FIG. 3, will become close to two frames (2.times.125 microseconds) at the maximum. This is twice the time required by a conventional single-memory system. Moreover, a signal passing through a number of such stages of time division switches would result in further amplification of the delay and a consequent deterioration of the quality of speech.